1. Field of the Invention
The invention relates to a monolithically integrated semiconductor memory with a matrix of identical memory cells arranged in rows of a set of row members and in columns or a set of column members, each in the form of an MOS-field effect transistor of the enhancement type and a storage capacity represented by an MOS-capacitor, wherein one comparator each and a comparison cell which is likewise represented by a memory cell of the above-mentioned type, is assigned to either each matrix column or each matrix row.
2. Description of the Prior Art
In the customary organization of such dynamic RAM-memories, assigned to each column of the memory matrix is one comparator which is effective as a differential amplifier, is located in the middle of the respective column, and is represented by a bistable flip-flop. One half of all the single-transistor memory cells provided per column is connected with its drain terminals to one input and the other half is connected in the same manner to the other input of the comparator. In each column there are furthermore provided two comparison cells, i.e. so-called dummy cells which are each connected to one of the two inputs of the associated comparator in the same manner as the memory cells proper. If, as customary, the usual designation "word line" is used for the line which is assigned to the respective individual matrix rows and is connected to the gate electrodes of the one-transistor memory cells belonging to the respective matrix row, and is arranged parallel to the rows, and the usual designation "bit line" is used for the line which is assigned to the individual matrix columns and is arranged parallel thereto, then the situation can be defined as follows: Each bit line BL of the memory matrix is cut in half and one half is connected to one signal input and the other half is connected to the other signal input of the respective corresponding comparator K. The number of single-transistor memory cells provided per column is accordingly also cut in half, one half being connected to one signal input and the other half to the other signal input of the comparator K, as can also be seen from FIG. 1 of the instant application yet to be described. The voltage-carrying terminal of the MOS-transistor of the individual single-transistor memory cell, facing away from the respective bit line BL, is connected through the storage capacitor of the respective cell to the reference potential (ground) or instead, to the other supply potential (V.sub.CC).
Such a memory circuit is shown, for instance, in the publication "1978 IEEE International Solid-State Circuits Conference", Pages 156 and 157 (see, for instance, FIG. 1 of this reference).
In the known memories with single-transistor memory cells, the comparator K is constructed as a rule of transistors of the same type as is used for the transistors of the single-transistor memory cells. The comparator K can therefore be jointly fabricated without an additional doping effort with the other transistors of the memory.
On the other hand, so-called CMOS-memories are known (see Proc. IEEE (July 1971), Pages 1044-1058; particularly Page 1054, FIG. 17) which use so-called six-transistor cells as memory cells. These memory cells are each composed of two inverters provided in CMOS-technology which in turn are formed of a series circuit of a p-channel transistor and an n-channel transistor (both of the enhancement type). The gates of these two complementary MOS-transistors of the individual inverter together form the signal input of the inverter, while its signal output is represented by a circuit point between the series-connected source-drain paths of the two transistors of the inverter. The two inverters are now connected, for instance, with the other terminal of their source-drain path to one pole, such as the positive pole of a d-c voltage source and there they receive the potential V.sub.CC, while the second terminal of the source-drain path of the respective second transistor, such as the n-channel transistor of the two inverters, is therefore connected to the other pole, such as the negative pole of the d-c voltage source. Finally, the two gates of the first inverter are connected to the signal output of the second inverter and the two gates of the second inverter of the memory cell are connected to the signal output of the first inverter, whereby the desired flip-flop effect and therefore, the storage ability of the cell, is secured. In conclusion it should further be noted that the terminals of the cell given by the outputs of the two inverters are each connected through the source-drain path of one n-channel MOS-field effect transistor of the enhancement type each, to one bit line controlling the respective flip-flop storage cell each, while the gates of these two field effect transistors are controlled through the word line assigned to the respective storage cell.